NSF/Intel Partnership on Foundational Microarchitecture Research

The summary for the NSF/Intel Partnership on Foundational Microarchitecture Research grant is detailed below. This summary states who is eligible for the grant, how much grant money will be awarded, current and past deadlines, Catalog of Federal Domestic Assistance (CFDA) numbers, and a sampling of similar government grants. Verify the accuracy of the data FederalGrants.com provides by visiting the webpage noted in the Link to Full Announcement section or by contacting the appropriate person listed as the Grant Announcement Contact. If any section is incomplete, please visit the website for the National Science Foundation, which is the U.S. government agency offering this grant.
NSF/Intel Partnership on Foundational Microarchitecture Research: The confluence of transistor scaling, increases in the number of architecture designs per process generation<a id="_anchor_1" name="_msoanchor_1" href="#_msocom_1"></a>, the slowing of clock frequency growth, and recent success in research exploiting Thread Level Parallelism (TLP) and Data Level Parallelism (DLP) all point to an increasing opportunity for innovative microarchitecture techniques and methodologies in delivering performance growth in the future. The NSF/Intel Partnership on Foundational Microarchitecture Research will support transformative microarchitecture research targeting improvements in instructions per cycle (IPC). This solicitation seeks microarchitecture technique innovations beyond simplistic, incremental scaling of existing microarchitectural structures. Specifically, FoMR seeks to advance research that has the following characteristics: (1) high IPC techniques ranging from microarchitecture to code generation; (2) &ldquo;microarchitecture turbo&rdquo; techniques that marshal chip resources and system memory bandwidth to accelerate sequential or single-threaded programs; and (3) techniques to support efficient compiler code generation. Advances in these areas promise to provide significant performance improvements to continue the cadence promised by Moore&rsquo;s Law. <div> <div> <div id="_com_1"> </div> </div> </div>
Federal Grant Title: NSF/Intel Partnership on Foundational Microarchitecture Research
Federal Agency Name: National Science Foundation (NSF)
Grant Categories: Science and Technology
Type of Opportunity: Discretionary
Funding Opportunity Number: 17-597
Type of Funding: Grant
CFDA Numbers: 47.070
CFDA Descriptions: Information not provided
Current Application Deadline: January 12th, 2018
Original Application Deadline: January 12th, 2018
Posted Date: September 8th, 2017
Creation Date: September 8th, 2017
Archive Date: February 11th, 2018
Total Program Funding: $3,000,000
Maximum Federal Grant Award:
Minimum Federal Grant Award: $500,000
Expected Number of Awards:
Cost Sharing or Matching: No
Last Updated: September 8th, 2017
Applicants Eligible for this Grant
Others (see text field entitled "Additional Information on Eligibility" for clarification.)
Additional Information on Eligibility
*Who May Submit Proposals: Proposals may only be submitted by the following: -Universities and Colleges - Universities and two- and four-year colleges (including community colleges) accredited in, and having a campus located in, the US acting on behalf of their faculty members. Such organizations also are referred to as academic institutions.
Link to Full Grant Announcement
NSF Publication 17-597
Grant Announcement Contact
NSF grants.gov support
grantsgovsupport@nsf.gov

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