Silicon-based Photonic Analog Signal Processing Engines with Reconfigurability (Si-PhASER)

The summary for the Silicon-based Photonic Analog Signal Processing Engines with Reconfigurability (Si-PhASER) grant is detailed below. This summary states who is eligible for the grant, how much grant money will be awarded, current and past deadlines, Catalog of Federal Domestic Assistance (CFDA) numbers, and a sampling of similar government grants. Verify the accuracy of the data FederalGrants.com provides by visiting the webpage noted in the Link to Full Announcement section or by contacting the appropriate person listed as the Grant Announcement Contact. If any section is incomplete, please visit the website for the DARPA Microsystems Technology Office, which is the U.S. government agency offering this grant.

Silicon-based Photonic Analog Signal Processing Engines with Reconfigurability (Si-PhASER): The purpose of this modification is to change the close date from 05/30/2009 to 06/01/2009. Original Description Below. DARPA is soliciting innovative research and development (R&D) proposals in the area of Silicon-based Photonic Analog Signal Processing Engines with Reconfigurability (Si-PhASER). The overall goal is the creation of novel silicon Photonic Integrated Circuit (PIC) elements and associated programmable filter array concepts, which can be fabricated in a CMOS-compatible process, and that enable high-throughput, low-power signal processors which overcome the limits of conventional electronic DSP technology. All administrative correspondence and questions on this solicitation, including requests for information on how to submit a proposal abstract or full proposal to this BAA, should be directed to [email protected]. See full BAA document attached.