Steep-subthreshold-slope Transistors for Electronics with Extremely-low Power (STEEP)

The summary for the Steep-subthreshold-slope Transistors for Electronics with Extremely-low Power (STEEP) grant is detailed below. This summary states who is eligible for the grant, how much grant money will be awarded, current and past deadlines, Catalog of Federal Domestic Assistance (CFDA) numbers, and a sampling of similar government grants. Verify the accuracy of the data provides by visiting the webpage noted in the Link to Full Announcement section or by contacting the appropriate person listed as the Grant Announcement Contact. If any section is incomplete, please visit the website for the DARPA Microsystems Technology Office, which is the U.S. government agency offering this grant.
Steep-subthreshold-slope Transistors for Electronics with Extremely-low Power (STEEP): PROGRAM OBJECTIVES AND DESCRIPTIONThe Defense Advanced Research Projects Agency is soliciting research proposals in the area of Steep-subthreshold-slope Transistors for Electronics with Extremely-low Power (STEEP). Proposed research should investigate the development of novel transistor technologies that will enable high-performance logic circuits with extremely low power consumption.The STEEP process developed must be consistent with achieving transistor subthreshold slopes below 60 mV/decade without performance penalty. Current CMOS technology uses transistors that work by electronically modulating a thermionic energy barrier. The high energy tail of the carrier (electron or hole) distribution function is responsible for the theoretical subthreshold slope limit for this type of switch of 60 mV/decade. Innovative approaches are sought to develop transistors based on non-thermionic switching physics.Additional information on the program objectives and structure is provided in Section I of the BAA 07-26 Proposer Information Pamphlet referenced below.PROGRAM SCOPEThe STEEP program will be conducted in three phases each having definite and measurable milestones, the most critical of which will be referred to as Go/No-Go (GNG) metrics. Each phase will culminate in a specified device and/or circuit demonstration which will serve to validate that the goals of the phase have been achieved. The period of performance for each of these phases and the milestone schedule will be proposed by offerors within their technical proposals and will be factors considered as part of the source selection process (see below). In general, a shorter phase is preferable, but each phase should clearly be adequate in duration to meet its objectives with reasonable risks and costs. Proposals should discuss plans for managing these factors.The three distinct phases of the program are: I. Steep-subthreshold-slope Transistor Development;II. Transistor Optimization & Circuit Integration; andIII. Yield Enhancement.TEAMING ARRANGEMENTSMultiple awards are anticipated. Collaborative efforts/teaming are encouraged. A web site ( has been established to facilitate formation of teaming arrangements between interested parties. Specific content, communications, networking, and team formation are the sole responsibility of the participants. Neither DARPA nor the Department of Defense (DoD) endorses the destination web site or the information and organizations contained therein, nor does DARPA or the DoD exercise any responsibility at the destination. This web site is provided consistent with the stated purpose of this BAA. Cost sharing is not required and is not an evaluation criterion but is encouraged where there is a reasonable probability of a potential commercial application related to the proposed research and development effort. The technical POC for this effort is Dr. Michael Fritze, fax: (703) 696-2206, electronic mail: PROPOSERS QUESTIONSA "Proposers Questions," website will be posted for BAA 07-26 on the DARPA, Microsystems Technology Office solicitations page ( If you would like to have a question answered and posted on this site, please send your question to the following address: INFORMATIONProposers must obtain a pamphlet entitled "BAA 07-26, Steep-subthreshold-slope Transistors for Electronics with Extremely-low Power (STEEP), Proposer Information Pamphlet" which provides further information on areas of interest, the submission, evaluation, and funding processes, proposal abstract formats, proposal formats, and other general information. This pamphlet may be obtained from the FedBizOpps website:, website:, World Wide Web (WWW) at URL or by fax, electronic mail, or mail request to the administrative contact address given below. Proposals not meeting the format described in the pamphlet may not be reviewed.In order to minimize unnecessary effort in proposal preparation and review, proposers are strongly encouraged to submit proposal abstracts in advance of full proposals. The proposal abstract must be submitted to on or before 4:00 p.m., local time, Friday, May 18, 2007. Proposal abstracts received after this time and date may not be reviewed. Upon review, DARPA will provide written feedback on the likelihood of a full proposal being selected and the time and date for submission of a full proposal. Proposal abstracts should not be submitted via - the "Apply" function will be available for submission of full proposals should University offerors choose to submit in this way. Proposers not submitting proposal abstracts must submit a full proposal to, or via for Universities wishing to use the "Apply" function, on or before 4:00 p.m., local time, Friday, July 27, 2007 in order to be considered during the initial round of selections; however, proposals received after this deadline may be received and evaluated up to one year from date of posting on FedBizOpps and Full proposals submitted after the due date specified in the BAA or due date otherwise specified by DARPA after review of proposal abstracts may be selected contingent upon the availability of funds. This notice, in conjunction with the BAA 07-26, Proposer Information Pamphlet, constitutes the total BAA. No additional information is available, nor will a formal RFP or other solicitation regarding this announcement be issued. Requests for the same will be disregarded. The Government reserves the right to select for award all, some, or none of the proposals received. All responsible sources capable of satisfying the Government's needs may submit a proposal which shall be considered by DARPA. Input on technical aspects of the proposals may be solicited by DARPA from non-Government consultants /experts who are bound by appropriate non-disclosure requirements. Non-Government technical consultants/experts will not have access to proposals that are labeled by their offerors as "Government Only". Historically Black Colleges and Universities (HBCUs), Minority Institutions (MIs), and Small and Small Disadvantaged Businesses are encouraged to submit proposals and join others in submitting proposals; however, no portion of this BAA will be set aside for these organizations participation due to the impracticality of reserving discrete or severable areas of research in deep ultraviolet avalanche photodetectors. All administrative correspondence and questions on this solicitation, including requests for information on how to submit a proposal abstract or full proposal to this BAA, should be directed to one of the administrative addresses below; e-mail or fax is preferred. DARPA intends to use electronic mail and fax for correspondence regarding BAA 07-26. Proposals and proposal abstracts may not be submitted by fax or e-mail; any so sent will be disregarded. DARPA encourages use of the WWW for retrieving the Proposer Information Pamphlet and any other related information that may subsequently be provided.EVALUATION CRITERIAEvaluation of proposals will be accomplished through a technical review of each proposal using the following criteria, which are listed in descending order of relative importance:(l) overall scientific and technical merit; (2) potential contribution and relevance to the DARPA mission; (3) relevance of intermediate milestones and GNG metrics; (4) realism of the proposed schedule; (5) plans and capability to accomplish technology transition; (6) offeror's capabilities and related experience; and (7) cost reasonableness and realism. Note: cost reasonableness and realism will only be significant in proposals which have significantly under or over-estimated the cost to complete their effort.The administrative addresses for this BAA are:Fax: (703) 696-2206 (Addressed to: DARPA/MTO, BAA 07-26), Electronic Mail: BAA07-26@darpa.milMail: DARPA/MTO, ATTN: BAA 07-26 3701 North Fairfax Drive Arlington, VA 22203-1714 This announcement and the Proposer Information Pamphlet may be retrieved via the WWW at URL in the solicitations area.
Federal Grant Title: Steep-subthreshold-slope Transistors for Electronics with Extremely-low Power (STEEP)
Federal Agency Name: DARPA Microsystems Technology Office
Grant Categories: Science and Technology
Type of Opportunity: Discretionary
Funding Opportunity Number: BAA07-26
Type of Funding: Procurement Contract Other Grant Cooperative Agreement
CFDA Numbers: 12.910
CFDA Descriptions: Research and Technology Development
Current Application Deadline: No deadline provided
Original Application Deadline: Jul 27, 2007
Posted Date: Apr 03, 2007
Creation Date: Mar 25, 2008
Archive Date: Mar 26, 2008
Total Program Funding:
Maximum Federal Grant Award: $0
Minimum Federal Grant Award: $0
Expected Number of Awards:
Cost Sharing or Matching: No
Applicants Eligible for this Grant
Unrestricted (i.e., open to any type of entity above), subject to any clarification in text field entitled "Additional Information on Eligibility"
Link to Full Grant Announcement
Information not provided
Grant Announcement Contact
Dr. Michael Fritze, Ph.D.
Program Manager
DARPA/MTO BAA Coordinator
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