NSF/Intel Partnership on Foundational Microarchitecture Research

The summary for the NSF/Intel Partnership on Foundational Microarchitecture Research grant is detailed below. This summary states who is eligible for the grant, how much grant money will be awarded, current and past deadlines, Catalog of Federal Domestic Assistance (CFDA) numbers, and a sampling of similar government grants. Verify the accuracy of the data FederalGrants.com provides by visiting the webpage noted in the Link to Full Announcement section or by contacting the appropriate person listed as the Grant Announcement Contact. If any section is incomplete, please visit the website for the National Science Foundation, which is the U.S. government agency offering this grant.
NSF/Intel Partnership on Foundational Microarchitecture Research: The confluence of transistor scaling, increases in the number of architecture designs per process generation, the slowing of clock frequency growth, and recent success in research exploiting thread-level parallelism (TLP) and data-level parallelism (DLP) all point to an increasing opportunity for innovative microarchitecture techniques and methodologies in delivering performance growth in the future. The NSF/Intel Partnership on Foundational Microarchitecture Research will support transformative microarchitecture research targeting improvements in instructions per cycle (IPC). This solicitation seeks microarchitecture technique innovations beyond simplistic, incremental scaling of existing microarchitectural structures. Specifically, FoMR seeks to advance research that has the following characteristics: (1) high IPC techniques ranging from microarchitecture to code generation; (2) “microarchitecture turbo” techniques that marshal chip resources and system memory bandwidth to accelerate sequential or single-threaded programs; and (3) techniques to support efficient compiler code generation. Advances in these areas promise to provide significant performance improvements that continue the trends characterized by Moore's Law.
Federal Grant Title: NSF/Intel Partnership on Foundational Microarchitecture Research
Federal Agency Name: National Science Foundation (NSF)
Grant Categories: Science and Technology
Type of Opportunity: Discretionary
Funding Opportunity Number: 18-588
Type of Funding: Grant
CFDA Numbers: 47.070
CFDA Descriptions: Information not provided
Current Application Deadline: November 28th, 2018
Original Application Deadline: November 28th, 2018
Posted Date: August 30th, 2018
Creation Date: August 30th, 2018
Archive Date: December 28th, 2018
Total Program Funding: $2,500,000
Maximum Federal Grant Award:
Minimum Federal Grant Award: $500,000
Expected Number of Awards:
Cost Sharing or Matching: No
Last Updated: August 30th, 2018
Applicants Eligible for this Grant
Others (see text field entitled "Additional Information on Eligibility" for clarification.)
Additional Information on Eligibility
*Who May Submit Proposals: Proposals may only be submitted by the following: -Institutions of Higher Education (IHEs) - Two- and four-year IHEs (including community colleges) accredited in, and having a campus located in the US, acting on behalf of their faculty members.Special Instructions for International Branch Campuses of US IHEs: If the proposal includes funding to be provided to an international branch campus of a US institution of higher education (including through use of subawards and consultant arrangements), the proposer must explain the benefit(s) to the project of performance at the international branch campus, and justify why the project activities cannot be performed at the US campus.
Link to Full Grant Announcement
NSF Publication 18-588
Grant Announcement Contact
NSF grants.gov support
[email protected]

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